Conventional methods for fabricating silicon carbide thyristors and gate turn-off thyristors include utilizing an all-epitaxial growth technique to fabricate each layer of the device. This epitaxial growth involves doping the crystal during crystal growth. This method has been the only method used for silicon carbide (SiC) thyristor fabrication. This invention is a new method for forming one or more doped layers using ion-implantation in the fabrication of thyristors after the crystal structure has been formed.
Advances in the semiconductor industry continue to be desired to address demand for semiconductor devices capable of high performance and low power consumption in a wide variety of applications. In one or more applications, enhanced high-voltage semiconductor devices such as, enhanced Schottky diodes, p-i-n diodes, insulated-gate bipolar transistors (IGBT), bipolar junction transistors (BJTs), etc., may be desired for, for instance, high-speed power switching applications.
This technology relates to high electron mobility transistors (HEMT). In conventional off-type HEMTs, a large amount of gate threshold voltage variation is often found. Transistors according to this technology include a p-type region, a barrier region, an insulation film, a gate electrode, and a channel region. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region.
This technology provides an improved MOSFET structure for power switching applications. An n- GaN reduced surface field (RESURF) region is created using epitaxial growth and selective etching of an n- drift layer. This is followed by ion implantation to achieve n GaN contact regions for the source and drain. This avoids the difficulties in controlling doping levels, leakage current, and electron mobility when using ion implantation alone to achieve the two different doping zones.
Conventional laterla trench-based components, such as trench lateral transistors, typically have a substantial undesirable capacitance related to the overlap of gate and drain electrodes in the same trench. Particularly, many trench-type lateral transistors are fabricated with the gate and the drain formed in the same trench, typically separated by an oxide layer. The overlap of the gate and drain regions results in a parasitic gate-to-drain capacitance, which can damage frequency response.
Silicon Carbide (SiC) has long been recognized as the choice for high voltage, high temperature, and high power applications. To achieve optimum design in SiC power devices, a varying charge in the lateral direction should be introduced. To f orm a junction termination extension (JTE) in SiC, different implant doses into multiple spaced zones can be used to create a non-uniform implant profile extending away from a junction termination. However, multiple implantation steps increase process cycle time, complexity, and fabrication cost.