Current DRAM chips can ensure error-free data storage (except for radiation-induced soft errors), which largely simplifies the overall computing system design. Each DRAM cell contains one transistor and one capacitor. Unfortunately, it becomes increasingly challenging to maintain the sufficiently large capacitance (hence error-free data storage). It has become clear that STT-RAM has the true potential to complement or even replace DRAM as the main memory in computing systems. However, STT-RAM cannot achieve comparable bit cost as DRAM. This solution provides strong memory error tolerance for memory devices having weak memory cells, thus addressing difficulties of conventional memory scaling under the error-free data storage constraints. The system includes a weak cell manager for determining andor storing weak cell location information; and three integrated processes for handling weak memory cells. The three processes include a virtual repair module for handling memory addresses known to have a very large number of weak cells; an address check module for performing address (e.g., table, database, etc.) look-ups; and a coding module for providing error correction coding and decoding operations. The described approach can be implemented with minimal overhead in terms of storage redundancy, memory access latency and energy consumption. By effectively relaxing the error-free data storage constraint, this approach can economically enables memory technology scaling towards 20 nm and below.