Current DRAM chips can ensure error-free data storage (except for radiation-induced soft errors), which largely simplifies the overall computing system design. Each DRAM cell contains one transistor and one capacitor. Unfortunately, it becomes increasingly challenging to maintain the sufficiently large capacitance (hence error-free data storage). It has become clear that STT-RAM has the true potential to complement or even replace DRAM as the main memory in computing systems. However, STT-RAM cannot achieve comparable bit cost as DRAM.
To implement hybrid nanodevices consisting of nanowire crossbars on top of a CMOS backplane, the challenge is to interface between the relatively coarse features of the CMOS domain and the dense nanowires above. Such an interface can be realised through a microwire to nanowire demultiplexer. This technology provides a hybrid demultiplexer architecture that combines both resistor and field effect transistor (FET) devices.