Solid state radiation detectors, such as neutron detectors and gamma ray detectors, have been proposed as alternatives to gas-tube based detectors. Radiation-detecting hetero-structures may be formed by using physical etching processes, such as reactive ion etching (RIE) to form trenches in a semiconductor substrate, followed by using chemical vapor deposition (CVD) to deposit radiation-detecting material within the formed trenches.

Conventional methods for fabricating silicon carbide thyristors and gate turn-off thyristors include utilizing an all-epitaxial growth technique to fabricate each layer of the device. This epitaxial growth involves doping the crystal during crystal growth. This method has been the only method used for silicon carbide (SiC) thyristor fabrication. This invention is a new method for forming one or more doped layers using ion-implantation in the fabrication of thyristors after the crystal structure has been formed.

This technology relates to neutron-detecting structures and methods of fabrication. Efficient solid-state neutron-detectors with large detecting surfaces and low gamma sensitivity are desired for detecting and preventing proliferation of special nuclear materials (SNMs). Unfortunately, available neutron-detectors are limited, for instance, by size, weight, high bias voltage requirements, andor cost due, for instance, to limited supply of enriched helium (3He) gas, which is currently employed in most neutron-detectors.

This technology relates to semiconductor devices and growth techniques in the field of III-N semiconductors. For example, the technology provides a semiconductor device with a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer has at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, and at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure.

To implement hybrid nanodevices consisting of nanowire crossbars on top of a CMOS backplane, the challenge is to interface between the relatively coarse features of the CMOS domain and the dense nanowires above. Such an interface can be realised through a microwire to nanowire demultiplexer. This technology provides a hybrid demultiplexer architecture that combines both resistor and field effect transistor (FET) devices.

This technology relates to high electron mobility transistors (HEMT). In conventional off-type HEMTs, a large amount of gate threshold voltage variation is often found. Transistors according to this technology include a p-type region, a barrier region, an insulation film, a gate electrode, and a channel region. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region.

This technology provides an improved MOSFET structure for power switching applications. An n- GaN reduced surface field (RESURF) region is created using epitaxial growth and selective etching of an n- drift layer. This is followed by ion implantation to achieve n GaN contact regions for the source and drain. This avoids the difficulties in controlling doping levels, leakage current, and electron mobility when using ion implantation alone to achieve the two different doping zones.

Conventional laterla trench-based components, such as trench lateral transistors, typically have a substantial undesirable capacitance related to the overlap of gate and drain electrodes in the same trench. Particularly, many trench-type lateral transistors are fabricated with the gate and the drain formed in the same trench, typically separated by an oxide layer. The overlap of the gate and drain regions results in a parasitic gate-to-drain capacitance, which can damage frequency response.