This technology relates to visually-guided multiprobe microassembly for assembling micro-electromechanical (MEMS) devices from multiple parts that are assembled rather than using bulk-processes to produce devices monolithically. Current production technologies primarily use a single wafer that is process chemically to produce finished devices. While this is useful for many devices, it results in mechanical regions that exist primarily in the plane and do not have fully spatial mechanisms without significant depth of stacked parts.

This technology relates to high electron mobility transistors (HEMT). In conventional off-type HEMTs, a large amount of gate threshold voltage variation is often found. Transistors according to this technology include a p-type region, a barrier region, an insulation film, a gate electrode, and a channel region. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region.

This technology provides an improved MOSFET structure for power switching applications. An n- GaN reduced surface field (RESURF) region is created using epitaxial growth and selective etching of an n- drift layer. This is followed by ion implantation to achieve n GaN contact regions for the source and drain. This avoids the difficulties in controlling doping levels, leakage current, and electron mobility when using ion implantation alone to achieve the two different doping zones.

Conventional laterla trench-based components, such as trench lateral transistors, typically have a substantial undesirable capacitance related to the overlap of gate and drain electrodes in the same trench. Particularly, many trench-type lateral transistors are fabricated with the gate and the drain formed in the same trench, typically separated by an oxide layer. The overlap of the gate and drain regions results in a parasitic gate-to-drain capacitance, which can damage frequency response.

For many decades, dry processing techniques, such as physical vapor deposition (PVD), have played a dominant role in integrated circuit metallization processes. During microelectronic device fabrication, films are often deposited on non-planar surfaces. The surface topography that wafers exhibit at various steps in the fabrication process arise from patterned features related to, for example, trenches andor vias.

Silicon Carbide (SiC) has long been recognized as the choice for high voltage, high temperature, and high power applications. To achieve optimum design in SiC power devices, a varying charge in the lateral direction should be introduced. To f orm a junction termination extension (JTE) in SiC, different implant doses into multiple spaced zones can be used to create a non-uniform implant profile extending away from a junction termination. However, multiple implantation steps increase process cycle time, complexity, and fabrication cost.

This invention is directed to a novel non-destructive method to remove excess layers of copper from microchip interconnect-metallization processing, allowing copper to be used in place of aluminum. The new method, an Electro-Chemical Planarization process, is a means of removing the copper in an electrolysis-designed solution bath without damaging the thin-film and interconnect surfaces. The process addresses the damages incurred by conventional CMP allowing for electron-migration into the insulative film layers leading to the eventual short-circuiting within the microchip devices.