Todays integrated circuits often can include millions of integrated components and devices. However, for a given product, it sometimes is not possible to achieve on one chip all of the circuitry required. A major challenge then becomes the interconnection of the circuitry on mulitple chips or substrates while keeping the connection resistance low and path lengths short to minimize inductive and capacitive effects, permitting high speed operation. Thus, a structure and method of forming compact integrated circuit assemblies and interconnections is needed.
Solid state radiation detectors, such as neutron detectors and gamma ray detectors, have been proposed as alternatives to gas-tube based detectors. Radiation-detecting hetero-structures may be formed by using physical etching processes, such as reactive ion etching (RIE) to form trenches in a semiconductor substrate, followed by using chemical vapor deposition (CVD) to deposit radiation-detecting material within the formed trenches.
This invention is directed to a method and apparatus for growing a multi-component single crystal boules that provides high quality and growth rate by growing the crystal from a multi-component melt, such as a ternary, quaternary or higher order melt. In the past, only binary compounds such as GaAs) could be commercially produced by directional solidification from melts, while compounds with more than two components resulted in a high density of defects.
Currently, the most common semiconductor dielectric is silicon dioxide (SiO2), which has a dielectric constant of about 4.0. There is a substantial interest in materials with low dielectric constants that can replace SiO2-based insulators as inter layer dielectrics (ILD). This invention is directed to a new process for the preparation of low dielectric constant films. The sol-gel process employs a hyperbranched polycarbosilane precursor that is applied to a substrate by spin coating.
Atomic layer deposition (ALD) is an ideal technique for fabricating thin layers requiring precision-controlled nanoscale film thickness. It is a type of chemical vapor deposition (CVD), wherein a film is built up through deposition of multiple ultra thin layers of atomic level controllability, with the thickness of the ultimate film being determined by the number of layers deposited.
Conventional methods for fabricating silicon carbide thyristors and gate turn-off thyristors include utilizing an all-epitaxial growth technique to fabricate each layer of the device. This epitaxial growth involves doping the crystal during crystal growth. This method has been the only method used for silicon carbide (SiC) thyristor fabrication. This invention is a new method for forming one or more doped layers using ion-implantation in the fabrication of thyristors after the crystal structure has been formed.
This technology relates to neutron-detecting structures and methods of fabrication. Efficient solid-state neutron-detectors with large detecting surfaces and low gamma sensitivity are desired for detecting and preventing proliferation of special nuclear materials (SNMs). Unfortunately, available neutron-detectors are limited, for instance, by size, weight, high bias voltage requirements, andor cost due, for instance, to limited supply of enriched helium (3He) gas, which is currently employed in most neutron-detectors.
This technology relates to semiconductor devices and growth techniques in the field of III-N semiconductors. For example, the technology provides a semiconductor device with a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer has at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, and at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure.
To implement hybrid nanodevices consisting of nanowire crossbars on top of a CMOS backplane, the challenge is to interface between the relatively coarse features of the CMOS domain and the dense nanowires above. Such an interface can be realised through a microwire to nanowire demultiplexer. This technology provides a hybrid demultiplexer architecture that combines both resistor and field effect transistor (FET) devices.
An edge illuminated photovoltaic device is a photovoltaic device in which light illuminates a p-n junction through the edge of the device (i.e. in the direction substantially non-parallel) to the direction defined by the devices electrical contacts to the outer surface. While these devices are advantageous, they are yet to achieve the high efficiency and low cost required for commerical viability. This invention relates to the fabrication of horizontally stacked, p-n junction type semiconductor devices for photovoltaic energy conversion via edge illumination.