Todays integrated circuits often can include millions of integrated components and devices. However, for a given product, it sometimes is not possible to achieve on one chip all of the circuitry required. A major challenge then becomes the interconnection of the circuitry on mulitple chips or substrates while keeping the connection resistance low and path lengths short to minimize inductive and capacitive effects, permitting high speed operation. Thus, a structure and method of forming compact integrated circuit assemblies and interconnections is needed.
Currently, the most common semiconductor dielectric is silicon dioxide (SiO2), which has a dielectric constant of about 4.0. There is a substantial interest in materials with low dielectric constants that can replace SiO2-based insulators as inter layer dielectrics (ILD). This invention is directed to a new process for the preparation of low dielectric constant films. The sol-gel process employs a hyperbranched polycarbosilane precursor that is applied to a substrate by spin coating.
This technology relates to a full spectrum broad wavelength emission white light source fabricated using a graded composition optically clear substrate that enables high efficiency, high flux, narrow or wide spectral width, large area, low cost LEDs with peak emission wavelength in the range of visible wavelength range from 400-750 nm.
This technology relates to an ultra high efficient LED system with the capability to modify an LEDs radiation pattern by changing its physical dimension-emission beam shape. The ultra high efficiency and redistribution of light has been achieved without the use of a back reflector. The ultra high efficiency can be controlled by changing the size of the nanorods within the design. These features can be very useful for bio-sensing and bio-imaging applications.
This technology relates to visually-guided multiprobe microassembly for assembling micro-electromechanical (MEMS) devices from multiple parts that are assembled rather than using bulk-processes to produce devices monolithically. Current production technologies primarily use a single wafer that is process chemically to produce finished devices. While this is useful for many devices, it results in mechanical regions that exist primarily in the plane and do not have fully spatial mechanisms without significant depth of stacked parts.
For many decades, dry processing techniques, such as physical vapor deposition (PVD), have played a dominant role in integrated circuit metallization processes. During microelectronic device fabrication, films are often deposited on non-planar surfaces. The surface topography that wafers exhibit at various steps in the fabrication process arise from patterned features related to, for example, trenches andor vias.
Silicon Carbide (SiC) has long been recognized as the choice for high voltage, high temperature, and high power applications. To achieve optimum design in SiC power devices, a varying charge in the lateral direction should be introduced. To f orm a junction termination extension (JTE) in SiC, different implant doses into multiple spaced zones can be used to create a non-uniform implant profile extending away from a junction termination. However, multiple implantation steps increase process cycle time, complexity, and fabrication cost.