Todays integrated circuits often can include millions of integrated components and devices. However, for a given product, it sometimes is not possible to achieve on one chip all of the circuitry required. A major challenge then becomes the interconnection of the circuitry on mulitple chips or substrates while keeping the connection resistance low and path lengths short to minimize inductive and capacitive effects, permitting high speed operation. Thus, a structure and method of forming compact integrated circuit assemblies and interconnections is needed.


This invention is directed to a method and apparatus for growing a multi-component single crystal boules that provides high quality and growth rate by growing the crystal from a multi-component melt, such as a ternary, quaternary or higher order melt. In the past, only binary compounds such as GaAs) could be commercially produced by directional solidification from melts, while compounds with more than two components resulted in a high density of defects.

Low dielectric constant films derived by sol-gel processing of a hyperbranched polycarbosilane

Currently, the most common semiconductor dielectric is silicon dioxide (SiO2), which has a dielectric constant of about 4.0. There is a substantial interest in materials with low dielectric constants that can replace SiO2-based insulators as inter layer dielectrics (ILD). This invention is directed to a new process for the preparation of low dielectric constant films. The sol-gel process employs a hyperbranched polycarbosilane precursor that is applied to a substrate by spin coating.


Atomic layer deposition (ALD) is an ideal technique for fabricating thin layers requiring precision-controlled nanoscale film thickness. It is a type of chemical vapor deposition (CVD), wherein a film is built up through deposition of multiple ultra thin layers of atomic level controllability, with the thickness of the ultimate film being determined by the number of layers deposited.

Edge Illumination Photovoltaic Devices and Methods of Making Same

An edge illuminated photovoltaic device is a photovoltaic device in which light illuminates a p-n junction through the edge of the device (i.e. in the direction substantially non-parallel) to the direction defined by the devices electrical contacts to the outer surface. While these devices are advantageous, they are yet to achieve the high efficiency and low cost required for commerical viability. This invention relates to the fabrication of horizontally stacked, p-n junction type semiconductor devices for photovoltaic energy conversion via edge illumination.

Probe-based High Precision Spatial Orientation Control and Assembly of Parts for Microassembly using Computer Vision

This technology relates to visually-guided multiprobe microassembly for assembling micro-electromechanical (MEMS) devices from multiple parts that are assembled rather than using bulk-processes to produce devices monolithically. Current production technologies primarily use a single wafer that is process chemically to produce finished devices. While this is useful for many devices, it results in mechanical regions that exist primarily in the plane and do not have fully spatial mechanisms without significant depth of stacked parts.

Enhanced Step Coverage of Thin Films on Patterned Substrates by Oblique Angle Physical Vapor Deposition

For many decades, dry processing techniques, such as physical vapor deposition (PVD), have played a dominant role in integrated circuit metallization processes. During microelectronic device fabrication, films are often deposited on non-planar surfaces. The surface topography that wafers exhibit at various steps in the fabrication process arise from patterned features related to, for example, trenches andor vias.

New Technique for Introducing Varying Lateral Charge in Multiple Zone Junction Termination Extension of Semiconductor Devices

Silicon Carbide (SiC) has long been recognized as the choice for high voltage, high temperature, and high power applications. To achieve optimum design in SiC power devices, a varying charge in the lateral direction should be introduced. To f orm a junction termination extension (JTE) in SiC, different implant doses into multiple spaced zones can be used to create a non-uniform implant profile extending away from a junction termination. However, multiple implantation steps increase process cycle time, complexity, and fabrication cost.


This invention is directed to a novel non-destructive method to remove excess layers of copper from microchip interconnect-metallization processing, allowing copper to be used in place of aluminum. The new method, an Electro-Chemical Planarization process, is a means of removing the copper in an electrolysis-designed solution bath without damaging the thin-film and interconnect surfaces. The process addresses the damages incurred by conventional CMP allowing for electron-migration into the insulative film layers leading to the eventual short-circuiting within the microchip devices.