Conventional methods for fabricating silicon carbide thyristors and gate turn-off thyristors include utilizing an all-epitaxial growth technique to fabricate each layer of the device. This epitaxial growth involves doping the crystal during crystal growth. This method has been the only method used for silicon carbide (SiC) thyristor fabrication. This invention is a new method for forming one or more doped layers using ion-implantation in the fabrication of thyristors after the crystal structure has been formed.
This technology relates to highly sensitive and large area optical sensor arrays with smart control that feature wireless operation. The optical sensors convert sensed illumination into a corresponding impedance (e.g., capacitance, inductance, etc.). The resulting impedance can then be easily integrated into a wireless signal generator (e.g., an LC or tank circuit), such that a characteristic of the illumination (e.g., intensity, wavelength, etc.) can be translated into a wireless output.
This technology relates to neutron-detecting structures and methods of fabrication. Efficient solid-state neutron-detectors with large detecting surfaces and low gamma sensitivity are desired for detecting and preventing proliferation of special nuclear materials (SNMs). Unfortunately, available neutron-detectors are limited, for instance, by size, weight, high bias voltage requirements, andor cost due, for instance, to limited supply of enriched helium (3He) gas, which is currently employed in most neutron-detectors.
This technology provides an LED design that can greatly improve polarization selectivity, 10:1, resulting in greater efficiency of the LED. The technology lies within a photonic crystal bi-refringent polarization rotator and an oxide spacer. The design blue-shifts transmission, which greatly improves overall efficiency of the LED by recycling wasted light and increasing polarization selectivity. Applications include: backlight units of liquid crystal displays, low noise sensing and high-contrast bio-imaging.
Semiconductor nanoparticles (also called quantum dots or nanocrystals) are generally used a lasing medium in a laser, as fluorescent tags in biological testing methods, and as electronics devices. However, these nanoparticles traditionally have high production costs and the methods used for synthesis are extremely toxic at high temperatures, posing safety risks during mass production. Additionally, it has been difficult to form nanoparticles of uniform size. This invention is directed to semiconductor nanoparticles having an elementally passivated surface.
This technology relates to high electron mobility transistors (HEMT). In conventional off-type HEMTs, a large amount of gate threshold voltage variation is often found. Transistors according to this technology include a p-type region, a barrier region, an insulation film, a gate electrode, and a channel region. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region.
This technology provides an improved MOSFET structure for power switching applications. An n- GaN reduced surface field (RESURF) region is created using epitaxial growth and selective etching of an n- drift layer. This is followed by ion implantation to achieve n GaN contact regions for the source and drain. This avoids the difficulties in controlling doping levels, leakage current, and electron mobility when using ion implantation alone to achieve the two different doping zones.
Conventional laterla trench-based components, such as trench lateral transistors, typically have a substantial undesirable capacitance related to the overlap of gate and drain electrodes in the same trench. Particularly, many trench-type lateral transistors are fabricated with the gate and the drain formed in the same trench, typically separated by an oxide layer. The overlap of the gate and drain regions results in a parasitic gate-to-drain capacitance, which can damage frequency response.
Isolating individual components of nanoscale architectures comprised of thin films or nanostructures, without significantly impacting their functionalities, is a critical challenge in micro- and nano-scale device fabrication. One example that illustrates this challenge is seen in Cu interconnect structures for nanometer devices. These devices use interfacial barrier nanolayers to isolate copper layers from dielectric layers.