Todays integrated circuits often can include millions of integrated components and devices. However, for a given product, it sometimes is not possible to achieve on one chip all of the circuitry required. A major challenge then becomes the interconnection of the circuitry on mulitple chips or substrates while keeping the connection resistance low and path lengths short to minimize inductive and capacitive effects, permitting high speed operation. Thus, a structure and method of forming compact integrated circuit assemblies and interconnections is needed. This invention provides a method for combining two chips in a face-to-face three dimensional configuration that support device interconnections and maintains low inductive, capacitive and resistive coupling between devices on the chips.